FPGA Programmable Delay Logic
A parameterized SystemVerilog design that evolves one cycle-delay contract across shift-register, circular-queue, and memory-based Driver/Checker architectures.
Read case studyEngineering Portfolio
Projects I designed and analyzed across FPGA, radar, biomedical AI, embedded systems, systems engineering, and coursework.
A parameterized SystemVerilog design that evolves one cycle-delay contract across shift-register, circular-queue, and memory-based Driver/Checker architectures.
Read case studyAligns ECG, SCG, and non-contact FMCW radar on a beat-relative axis and analyzes morphology-based AO/AC candidate timing.
Read case studyTraces timing integrity from earlobe PPG acquisition through IBI/HRV feature construction and CNN+Transformer classification.
Read case studyIntegrates PPG and EAR vision across a two-node Raspberry Pi sensing/analysis architecture with TCP/IP and GPIO/I²C alarm paths.
Read case studyEducational case studies that define requirements and calculate quantitative trade-offs and FMEA for Counter-UAS, EW jammer, and KF-21 reliability scenarios.
Read case studyCourse-by-course work on VHDL simulation, transformer calculations, power-flow debugging, motor control, RF networks, and an AESA-SAR proposal.
Read case studyA PCB inspection project that connects F411-board visual intake, quality gating, ROI alignment, PatchCore/FR-PatchCore, DINOv3-style features, paper figures, and public project publishing.
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