Hardware Reverse Engineering · Mixed-Signal · System Integration

Legacy Embedded System Architecture & Mixed-Signal Interfaces

CPU, memory, video, storage, and communication analysis of the Macintosh Color Classic and Olympic-S, with a BlueSCSI/Raspberry Pi bridge design.

Hardware/manual analysis and measurement plan

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Legacy Embedded Systems

Color Classic, Olympic-S · interfaces

Architecture and interfaces Technical records

Problem

Safely connecting computers, CRTs, cassette storage, and SCSI devices from different generations requires validating signal topology, levels, termination, and protocol rather than matching connector shapes.

Architecture

The architecture maps Olympic-S Z80, 64-KB memory, TTL/glue logic, RGBS, cassette, and 64-contact bus alongside the Color Classic 68030, 10-MB DRAM, ADB, RS-422, and SCSI, with BlueSCSI/Pico-W and a Raspberry Pi backend as the modern data and validation layer.

Hardware and Software

MC68030
Z80-compatible CPU
RGBS
SCSI
ADB
RS-422
BlueSCSI
Raspberry Pi

Data Flow

Modern PC/Raspberry Pi → SD/BlueSCSI → SCSI bus → Color Classic HMI; Olympic-S RGBS/cassette/system bus → level, termination, and continuity checks → CRT, recorder, or MCU bridge.

Methodology

{"Applied five evidence levels"=>"direct observation, cross-check, document-confirmed, reasoned inference, and pending measurement"}
Cross-checked PCB markings, OS screens, source manuals, and connector photographs in functional-block and interface matrices
Defined bring-up order and hazards for power, video, storage, and communication paths

Results

Mapped the Color Classic 68030, 10-MB DRAM, SCSI, ADB, serial architecture, and major logic-board components
Documented the Olympic-S Z80-family CPU, 48-KB RAM, 16-KB ROM, DIN-5 RGBS, and 1200-bit/s cassette path
Produced a bridge architecture that separates the legacy HMI from the modern backend and prioritizes follow-up measurements

Architecture and result views

Validation diagram from Olympic-S video logic through DIN-5 sync, ground, and RGB pins to an RGB monitor or conversion path — Interface flow that validates RGBS topology, signal levels, and 75-ohm termination before connection

Five-level evidence table for legacy hardware, from direct observation through pending measurement — Evidence matrix separating photographs, functional history, source specifications, inference, and pending measurements

What I worked on

Mapped CPU, RAM, ROM, ASIC, TTL, and connector blocks on 68030- and Z80-era boards
Decomposed RGBS, DIN-5, SCSI, ADB, RS-422, and cassette interfaces into signal and electrical checks
Defined BlueSCSI, Pico-W, and Raspberry Pi data paths plus continuity, level, termination, and ripple tests

Code and results

A 23-page technical portfolio with hardware, PCB, and runtime photographs
Color Classic 10,240K boot screen and logic-board chip markings
Olympic-S manual specifications for 48-KB RAM, 16-KB ROM, 1200-bit/s cassette data, and DIN-5 RGBS

Design scope and next steps

Sources: hardware, PCB markings, OS screens, and original manuals. Follow-up tests: RGBS levels, termination, cable continuity, cassette SAVE/LOAD, and DaynaPORT TCP.

Project resources

Repository Project Pages

Color Classic and Olympic-S records map CPU, memory, storage, video, and communication layers. PCB markings, OS screens, and source manuals support the functional-block and interface tables.

The BlueSCSI/Raspberry Pi material covers a bridge data-path design and RGBS, SCSI, cassette, and TCP measurement plans.

Technical and hardware records