Patent · CES 2027
The public portfolio now reflects the completed Korean patent filing and the submitted CES 2027 Innovation Awards application.
KOREAN PATENT APPLICATION
Application No. 10-2026-0154726 · Filed August 18, 2026
Co-inventor · Jointly filed by the Dankook University Cheonan Campus Industry-Academic Cooperation Foundation and Hansono Co., Ltd.
CES 2027
ViScan CES 2027 Innovation Awards application submitted
Planned ViScan booth operation and live product demonstration
Profile
An undergraduate electrical engineering researcher focused on radar, vision AI, sensor fusion, and embedded signal processing, with FPGA RTL and digital verification as a secondary track.
At the Human & Systems Laboratory, I worked on concurrent ECG, SCG, and FMCW radar acquisition and aligned cardiac-cycle waveforms. The setup used a BGT60TR13C radar, STM32F411, and ESP-32S/MPU6050 reference paths. In Python, I compared radar phase with AO and AC candidate timing around ECG R-peaks.
For the ViScan smart mirror, I integrated camera and FMCW radar inputs into a pipeline covering presence detection, face sessions, pose-based AR guidance, and rPPG. I used YuNet/SFace face recognition and MediaPipe Pose, combined low-light, occlusion, and multi-person checks with BGT60TR13C presence and distance information, and defined state-transition conditions for each sensing stage. I plan to participate in ViScan booth operation and live demonstrations at CES 2027. The ViScan CES 2027 Innovation Awards application has also been submitted.
The core ViScan technology was filed in Korea under the title “Ultrasound-Based Smart Mirror Body Composition Analysis System” (portfolio translation of the Korean filing title). The Korean patent application number is 10-2026-0154726, filed on August 18, 2026. It was jointly filed by the Dankook University Cheonan Campus Industry-Academic Cooperation Foundation and Hansono Co., Ltd., and I participated as a co-inventor. This is a patent application, not a granted patent.
I wrote combinational, sequential, and parameterized RTL in VHDL and SystemVerilog. My testbenches separate drivers, checkers, and reference models, then compare input vectors against DUT outputs. I used Icarus, GHDL, Quartus, and ModelSim/Questa.
I also built PADS schematics and footprints and reviewed microstrip, Wilkinson divider, and branch-line hybrid S-parameters in Cadence. My coursework includes control, motor drives, power electronics, and electrical machines.
I am preparing primarily for radar signal processing, vision AI, sensor fusion, and embedded acquisition roles, with FPGA RTL and digital verification as a second track. I expect to graduate in February 2027 and can start work in January 2027.