FPGA · RTL · Digital Verification

FPGA Programmable Delay Logic

Three SystemVerilog delay architectures: shift register, circular queue, and memory. Icarus simulation, GTKWave waveforms, RTL, and testbenches.

Simulation · 31 / 32 cycles · 3 scenarios

⌘ Repository ↗ Project Page

Open the files

FPGA RTL

Three delay circuits · waveforms and RTL

Waveforms and schematics RTL, TB, and logs

Problem

Verify three delay structures against their testbenches and reference vectors, including distinct output timing and invalid-data behavior.

Architecture

Projects 1/2 select the Nth newest sample including the current edge and output zero when invalid. Project 3 registers the output after N periods and holds invalid data.

Hardware and Software

SystemVerilog
Icarus Verilog 14.0
GTKWave
VS Code

Data Flow

Parameters and input vectors → DUT and reference model → cycle-aligned checker → deterministic PASS/FAIL log.

Methodology

Preserved original DUT RTL hashes
Added independent history checkers for Projects 1/2; used the file-driven Driver/Checker for Project 3
Opened actual VCDs in GTKWave and captured RTL/TB in VS Code

Results

Project 1: 31 checked cycles PASS, 0 errors
Project 2: 32 checked cycles PASS, 0 errors
Project 3: 3 scenarios PASS — checked/valid 8/5, 14/4, 17/14

Architecture and result views

Project 1 — Actual GTKWave detail — Project 1 · Actual GTKWave detail · 2026-09-16

Project 1 — Actual GTKWave full — Project 1 · Actual GTKWave full · 2026-09-16

Project 1 — Actual VS Code RTL and testbench — Project 1 · Actual VS Code RTL and testbench · 2026-09-16

Project 1 — RTL-derived gate/register schematic — Project 1 · RTL-derived gate/register schematic · 2026-09-16

Project 2 — Actual GTKWave detail — Project 2 · Actual GTKWave detail · 2026-09-16

Project 2 — Actual GTKWave full — Project 2 · Actual GTKWave full · 2026-09-16

Project 2 — Actual VS Code RTL and testbench — Project 2 · Actual VS Code RTL and testbench · 2026-09-16

Project 2 — RTL-derived gate/register schematic — Project 2 · RTL-derived gate/register schematic · 2026-09-16

Project 3 — Actual GTKWave scenario1 — Project 3 · Actual GTKWave scenario1 · 2026-09-16

Project 3 — Actual GTKWave scenario2 — Project 3 · Actual GTKWave scenario2 · 2026-09-16

Project 3 — Actual GTKWave scenario3 — Project 3 · Actual GTKWave scenario3 · 2026-09-16

Project 3 — Actual VS Code RTL and testbench — Project 3 · Actual VS Code RTL and testbench · 2026-09-16

Project 3 — RTL-derived gate/register schematic — Project 3 · RTL-derived gate/register schematic · 2026-09-16

What I worked on

Parameterized SystemVerilog RTL
Independent reference model
Self-checking testbench and deterministic regression

Code and results

Project 1: 31 checked cycles PASS, 0 errors
Project 2: 32 checked cycles PASS, 0 errors
Project 3: 3 scenarios PASS — checked/valid 8/5, 14/4, 17/14

Design scope and next steps

Run: Icarus Verilog 14.0, 2026-09-16. Diagrams: RTL logic. Synthesis, place-and-route, and PPA: separate stages.

Project resources

Repository Project Pages

Icarus Verilog run dated 2026-09-16: Project 1 passed 31 checked cycles, Project 2 passed 32 checked cycles, and Project 3 passed three scenarios. All error counts are zero.

The gallery contains GTKWave waveforms, VS Code RTL/testbench screens, and source-derived gate/register diagrams.

RTL, testbenches, VCDs, and run logs

The July 20/26-check regressions and September 31/32-cycle checks are separate runs.