FPGA · RTL · Digital Verification

FPGA Programmable Delay Logic

A parameterized SystemVerilog design that evolves one cycle-delay contract across shift-register, circular-queue, and memory-based Driver/Checker architectures.

Functional simulation rerun

⌘ Repository ↗ Project Page

Problem

The project implements one cycle-delay contract across multiple RTL architectures while independently checking latency and output equivalence.

Architecture

The architecture progresses from a shift register to a circular queue and a memory-based Driver/Checker, compared against an independent reference model.

Hardware and Software

SystemVerilog
Icarus Verilog
VHDL
GHDL
Quartus
ModelSim/Questa

Data Flow

Parameters and input vectors → DUT and reference model → cycle-aligned checker → deterministic PASS/FAIL log.

Methodology

Defined an RTL contract that remains stable across width, depth, and delay parameters
Built an independent reference model and self-checking testbench
Executed file-driven scenarios and architecture-equivalence regressions

Results

Project 1 passed 20 Icarus Verilog checks
Project 2 passed 26 architecture-equivalence checks
Project 3 passed three file-driven scenarios

01Problem

The project implements one cycle-delay contract across multiple RTL architectures while independently checking latency and...

02Architecture

The architecture progresses from a shift register to a circular queue and a memory-based Driver/Checker, compared against ...

03Method

Defined an RTL contract that remains stable across width, depth, and delay parameters

04Result

Project 1 passed 20 Icarus Verilog checks

A compact problem-to-result map generated from the project data used on this page.

Architecture and result views

File-driven simulation waveform and timing markers for the FPGA programmable delay logic — Dynamic-delay waveform produced from the Project 3 file input

What I worked on

Parameterized SystemVerilog RTL
Independent reference model
Self-checking testbench and deterministic regression

Code and results

I passed 20 Icarus Verilog tests in Project 1.
I passed 26 architecture-equivalence tests in Project 2.
All three file-driven scenarios in Project 3 matched the expected outputs.

Next steps

I completed functional simulation. Next, I plan to run Quartus synthesis and timing, power, and Fmax analysis, then summarize the PPA values from those reports.

Project resources

Repository Project Pages

I implemented the same cycle-delay behavior with three RTL architectures and compared each one against an independent reference model in a self-checking testbench. Quartus synthesis and timing analysis remain the next step.