SystemVerilog · RTL Architecture · Digital Verification

Programmable delay logic,
developed as verifiable architecture

One delay contract is implemented as a shift register, circular queue, and memory-based DUT. The portfolio includes actual Icarus Verilog 13.0 regression logs, VCD files, and rendered waveforms—not only design descriptions.

Inspect executed evidence English README

3 / 3 PASSproject functional regressions

46Project 1–2 self-checks

3Project 3 file scenarios

13.0Icarus Verilog version

Architecture Evolution

Same function, different engineering questions

Project 1 establishes data/valid alignment. Project 2 replaces whole-stage movement with one-slot writes. Project 3 adds repeatable file-driven stimulus and deterministic error reporting.

Architecture evolution across three FPGA delay-logic projects

Project 1 · Baseline

Shift register

Data and valid traverse equal depth; iDelay-1 selects the historical transaction.

Regression PASS

Project 2 · Scale

Circular queue

(write_ptr-iDelay) mod DEPTH and one-slot writes preserve the delay behavior.

Equivalence PASS

Project 3 · DV

Memory-based verification

Input Driver, DUT, and Output Checker compare data, valid, and final output count.

3 scenarios PASS

Brief-to-Architecture Redraws

Project briefs, redrawn for engineering review

Five pages across the three lecture PDFs were analyzed and reconciled with repository RTL and testbenches. These eight new diagrams are not source-slide captures; each is published as SVG with a PNG fallback.

Project 1 shift-register datapath and tap selection — P1 · data/valid pipeline and `iDelay=N → tap[N-1]`

Project 1 self-checking testbench architecture — P1 · stimulus, DUT, independent reference model, scoreboard

Project 1 expected timing contract — P1 · cycle contract with sparse valid and dynamic delay

Project 2 circular queue write pointer and read address — P2 · one-slot write and modulo read address

Project 2 shift-register and circular-queue architecture comparison — P2 · one delay contract, different state-update cost

Project 2 four controlled PPA configurations — P2 · Shift/Circular × DEPTH 10/100; numerical PPA remains BLOCKED

Project 3 file-driven verification architecture — P3 · input/register/output files with Driver, DUT, and Checker

Project 3 three-scenario execution flow — P3 · reset, continuous enable, and delay change under one checker

Key RTL

Structure and state policy

Every implementation treats data and valid as one transaction. Memory-coded designs leave the data array unreset and use valid state to prevent stale data from becoming observable.

Parallel data and valid shift-register paths

Circular queue write pointer and modulo read address

Memory-based programmable delay block diagram

File-driven Input Driver, DUT, and Output Checker flow

Executed Evidence

Waveforms rendered from actual runs

These are not expected-waveform illustrations. They are rendered directly from VCD files generated by Icarus Verilog 13.0 while executing RTL and testbenches from commit c356ade.

Project 1 shift-register regression PASS waveform — Project 1 · fixed, sparse-valid, and dynamic-delay traffic · 20 checks PASS

Project 2 shift-register and circular-queue equivalence PASS waveform — Project 2 · shift register = circular queue = independent reference · 26 checks PASS

Project 3 file-driven delay 3 to 5 change and Checker PASS waveform — Project 3 scenario 3 · delay 3→5 · 17 cycles, 14 valid outputs, Checker PASS

Validation Matrix

PASS and BLOCKED are separate states

Functional simulation is labeled PASS only where an executed log exists. Synthesis and numerical PPA remain BLOCKED because Quartus was not installed on the verification host.

Project	RTL	Simulation	Synthesis	PPA
1 · Shift Register	Reviewed	PASS Icarus 13.0 · 20 checks	BLOCKED Quartus unavailable	N/A
2 · Circular Queue	Reviewed	PASS 2 implementations + reference · 26 checks	BLOCKED Quartus unavailable	BLOCKED No Fit/Timing/Power reports
3 · Memory DV	Reviewed	PASS Scenarios 1–3 · Checker + Test PASS	BLOCKED Quartus unavailable	N/A

Project 1 Evidence

20 checks

Simulation log VCD

Project 2 Evidence

26 checks

Equivalence log VCD

Project 3 Evidence

3 scenarios

Logs + VCD Evidence manifest

PPA Boundary

Method prepared, numbers not claimed

Four DEPTH 10/100 projects share device, clock, optimization, virtual-pin, and toggle assumptions. Without Quartus Fit, Timing, and Power reports, no area, Fmax, or power advantage is published.

Four-case PPA method and BLOCKED numerical status

Numerical PPA: BLOCKED. The host scan found no quartus_sh, quartus_fit, quartus_sta, or quartus_pow. Blank CSV cells were not visualized and estimates were not fabricated.

Reproducibility

One command reruns all three projects

On Windows with PowerShell and Icarus Verilog 13.0, this command rebuilds the logs, VCD files, and JSON evidence manifest.

powershell -NoProfile -ExecutionPolicy Bypass -File .\scripts\run_all_verification.ps1

Verification summary Reproduction guide