FPGA Programmable Delay Logic

실제 GTKWave · VS Code 실행 화면 · 2026-09-16

Icarus Verilog 14.0 · GTKWave · VS Code · SystemVerilog

ProjectActual resultErrors
1 — Shift Register31 checked cycles PASS0
2 — Circular Queue32 checked cycles PASS0
3 — Memory + Registered Output3 scenarios: 8/5, 14/4, 17/14 checked/valid cycles PASS0

파형은 실제 GTKWave 창, 코드는 실제 VS Code 창을 캡처했습니다. 아래 구조도는 RTL 코드에서 도출해 별도로 그린 게이트·레지스터 구조입니다. 이번 실행에서는 Quartus·ModelSim 및 합성·PPA를 수행하지 않았습니다.

Project 1/2: tap N includes the current sampled edge; invalid output = 0. Project 3: registered output after N periods; invalid output holds its previous data.

Project 1 — Shift Register

RTL / Testbench / VCD / Logs / Reproduction

Project 1: Actual GTKWave window
Actual GTKWave window
Project 1: Actual VS Code: RTL and testbench
Actual VS Code: RTL and testbench
Project 1: RTL-derived gate/register schematic — separate drawing
RTL-derived gate/register schematic — separate drawing

gtkwave_full

Project 2 — Circular Queue

RTL / Testbench / VCD / Logs / Reproduction

Project 2: Actual GTKWave window
Actual GTKWave window
Project 2: Actual VS Code: RTL and testbench
Actual VS Code: RTL and testbench
Project 2: RTL-derived gate/register schematic — separate drawing
RTL-derived gate/register schematic — separate drawing

gtkwave_full

Project 3 — Memory + Registered Output

RTL / Testbench / VCD / Logs / Reproduction

Project 3: Actual GTKWave window
Actual GTKWave window
Project 3: Actual VS Code: RTL and testbench
Actual VS Code: RTL and testbench
Project 3: RTL-derived gate/register schematic — separate drawing
RTL-derived gate/register schematic — separate drawing

gtkwave_scenario1 · gtkwave_scenario2

Capture provenance · Verification manifest

Historical teaching diagrams and earlier regression

July 2026 archive (separate run)