Course record
Controller Logic Design
I revisit my VHDL sources, schematics, and waveforms from combinational logic through finite-state machines.
Unit numbers are a reading sequence reconstructed from the saved designs, not an attendance-week record.
12 Units
Weekly study sequence
- W01Boolean Logic and Digital RepresentationTruth tables · Boolean algebra · Logic gates
- W02Combinational Logic DesignMinterms and maxterms · Karnaugh maps · Logic minimization
- W03Full Adders and Ripple-Carry AddersSum and carry · One-bit full adder · Four-bit composition
- W04Decoders and MultiplexersThree-to-eight decoder · Eight-to-one multiplexer · Select signals
- W05Writing Combinational VHDLEntity and architecture · Concurrent assignments · Process sensitivity
- W06Sequential Logic and ClocksD flip-flops · Clock edges · Synchronous reset
- W07Registers and Shift RegistersParallel load · Left and right shift · Universal shift register
- W08FSM States and TransitionsState diagrams · State encoding · Next-state logic
- W09Mealy 101 Sequence DetectorMealy outputs · Overlapping detection · Three-state design
- W10VHDL Testbenches and WaveformsStimulus processes · Expected-value comparison · Assertions
- W11Synthesis and Timing ChecksRTL elaboration · Synthesis results · Critical paths
- W12Design Integration and Regression ChecksComponent binding · Port mapping · Self-checking simulation
How I use this hub
I open one unit at a time, restate the core terms, and compare equations, circuits, code, and saved results.