Week 10
VHDL Testbenches and Waveforms
I revisit my VHDL sources, schematics, and waveforms from combinational logic through finite-state machines.
What I connect in this unit
A stimulus process schedules input sequences, and expected-value comparison checks the design against a reference result. Assertions automate failures, while waveform reading still reveals transition order and delay.
Concept map
- Stimulus processes
- Expected-value comparison
- Assertions
- Waveform reading
Technical anchor
assert sum = expected_sum report "sum mismatch" severity error; reports an error only when the current vector disagrees with the reference sum.
How I review it
Iterate vectors containing boundary and ordinary cases, and use one deliberately wrong expected value to check whether the assertion identifies the correct instant.
Connection to the full course
Unit 10 of 12. Unit numbers are a reading sequence reconstructed from the saved designs, not an attendance-week record.