Week 11
Synthesis and Timing Checks
I revisit my VHDL sources, schematics, and waveforms from combinational logic through finite-state machines.
What I connect in this unit
RTL elaboration expands entities, generics, and hierarchy into a logic network, and synthesis maps it to target cells. Comparing the longest critical path with the clock constraint tests whether functionally correct RTL can meet the requested period.
Concept map
- RTL elaboration
- Synthesis results
- Critical paths
- Clock constraints
Technical anchor
If the requested clock period is 10 ns and the longest setup path is 11.2 ns, slack = 10 − 11.2 = −1.2 ns and timing is not met.
How I review it
Locate the top-level clock, startpoint, endpoint, and combinational delay in the synthesis report, confirm constraint units, and inspect the logic depth of any negative-slack path.
Connection to the full course
Unit 11 of 12. Unit numbers are a reading sequence reconstructed from the saved designs, not an attendance-week record.