Week 12
Design Integration and Regression Checks
I revisit my VHDL sources, schematics, and waveforms from combinational logic through finite-state machines.
What I connect in this unit
Component binding connects an instantiated block to its implementation, and port mapping aligns signal direction and width. After integration, self-checking simulation verifies hierarchy and traces any assertion failure back through source and waveform transitions.
Concept map
- Component binding
- Port mapping
- Self-checking simulation
- Source-to-waveform tracing
Technical anchor
Connecting a four-bit data_out port to a three-bit signal creates a width mismatch, so an intentional slice must be distinguished from an integration error.
How I review it
Compare generics, port widths, and directions for every instance, define regression vectors, and map each assertion name to its source line and waveform signal for diagnosis.
Connection to the full course
Unit 12 of 12. Unit numbers are a reading sequence reconstructed from the saved designs, not an attendance-week record.