Week 09
Mealy 101 Sequence Detector
I revisit my VHDL sources, schematics, and waveforms from combinational logic through finite-state machines.
What I connect in this unit
A Mealy detector derives output from both state and input, so it can assert detection in the cycle that completes 101. Three states remember prefixes 1 and 10, and overlapping detection preserves the final 1 as the start of another pattern.
Concept map
- Mealy outputs
- Overlapping detection
- Three-state design
- Transition tracing
Technical anchor
For input stream 10101, detect becomes one at the third and fifth bits, marking two overlapping occurrences of 101.
How I review it
Trace 000, 101, 10101, and 1101 bit by bit through the transition table, checking output timing and the state retained after detection.
Connection to the full course
Unit 9 of 12. Unit numbers are a reading sequence reconstructed from the saved designs, not an attendance-week record.