Week 03
Full Adders and Ripple-Carry Adders
I revisit my VHDL sources, schematics, and waveforms from combinational logic through finite-state machines.
What I connect in this unit
A one-bit full adder combines two operand bits and carry-in to produce sum and carry-out. Cascading four cells forms a ripple-carry adder whose completion time is governed by carry propagation through the stages.
Concept map
- Sum and carry
- One-bit full adder
- Four-bit composition
- Carry propagation
Technical anchor
S = A ⊕ B ⊕ Cin and Cout = A·B + Cin·(A ⊕ B); adding 1111₂ and 0001₂ forces a carry through all four stages.
How I review it
Check sum and final carry for 0000+0000, 0101+0011, and 1111+0001, then trace each intermediate carry in the last case.
Connection to the full course
Unit 3 of 12. Unit numbers are a reading sequence reconstructed from the saved designs, not an attendance-week record.