Week 04
Decoders and Multiplexers
I revisit my VHDL sources, schematics, and waveforms from combinational logic through finite-state machines.
What I connect in this unit
A three-to-eight decoder expands one select code into a one-hot output, whereas an eight-to-one multiplexer uses the same select width to route one of eight inputs. Enable lines and upper select bits support hierarchical composition.
Concept map
- Three-to-eight decoder
- Eight-to-one multiplexer
- Select signals
- Hierarchical composition
Technical anchor
With select code S2S1S0 = 101, only decoder output D5 is active and the multiplexer output equals I5.
How I review it
Sweep select codes 000 through 111 to check the one-hot condition and routed input, then verify that a disabled lower-level block remains inactive.
Connection to the full course
Unit 4 of 12. Unit numbers are a reading sequence reconstructed from the saved designs, not an attendance-week record.