Week 05
Writing Combinational VHDL
I revisit my VHDL sources, schematics, and waveforms from combinational logic through finite-state machines.
What I connect in this unit
The entity defines the circuit boundary through ports and types, and the architecture describes behavior. Concurrent assignments suit direct logic, while a combinational process must include every read signal in its sensitivity list and use synthesizable constructs.
Concept map
- Entity and architecture
- Concurrent assignments
- Process sensitivity
- Synthesizable constructs
Technical anchor
The statement with sel select y <= a when '0', b when others; expresses a two-to-one multiplexer as one concurrent assignment.
How I review it
Check that every input transition updates the output and that each process path assigns a default value so no unintended latch is inferred.
Connection to the full course
Unit 5 of 12. Unit numbers are a reading sequence reconstructed from the saved designs, not an attendance-week record.