Week 06
Sequential Logic and Clocks
I revisit my VHDL sources, schematics, and waveforms from combinational logic through finite-state machines.
What I connect in this unit
A D flip-flop transfers D to Q only on the selected clock edge, creating a time boundary around combinational logic. A synchronous reset is evaluated on that edge, and setup and hold intervals protect reliable sampling.
Concept map
- D flip-flops
- Clock edges
- Synchronous reset
- Setup and hold
Technical anchor
On rising_edge(clk), Q receives zero when reset is one and D otherwise; the synchronous reset therefore cannot change Q between clock edges.
How I review it
Draw D and reset transitions around a clock edge, verify that Q changes only at the edge, and mark the intervals that would violate setup or hold time.
Connection to the full course
Unit 6 of 12. Unit numbers are a reading sequence reconstructed from the saved designs, not an attendance-week record.