Week 07
Registers and Shift Registers
I revisit my VHDL sources, schematics, and waveforms from combinational logic through finite-state machines.
What I connect in this unit
A register groups D flip-flops for parallel loading, while selectable feedback paths shift bits left or right. A universal shift register needs explicit control priority when hold, shift, and load requests overlap.
Concept map
- Parallel load
- Left and right shift
- Universal shift register
- Control priority
Technical anchor
With priority load > shift_left > shift_right > hold, a clock edge with load asserted captures the parallel input regardless of the shift controls.
How I review it
Starting from 1010, apply left shift, right shift, and parallel load, then check the simultaneous load-and-shift case against the declared priority.
Connection to the full course
Unit 7 of 12. Unit numbers are a reading sequence reconstructed from the saved designs, not an attendance-week record.