Week 02
Combinational Logic Design
I revisit my VHDL sources, schematics, and waveforms from combinational logic through finite-state machines.
What I connect in this unit
Minterms and maxterms translate a truth table into canonical expressions, while a Karnaugh map combines adjacent terms to minimize the logic. Unequal propagation delays can still create a transient hazard in the reduced network.
Concept map
- Minterms and maxterms
- Karnaugh maps
- Logic minimization
- Propagation delay
Technical anchor
For F(A,B,C) = Σm(1,3,5,7), one four-cell Karnaugh-map group reduces the entire function to F = C.
How I review it
Compare all eight outputs of the canonical and minimized forms, then inspect transitions where one input change reaches the output through paths of different depth.
Connection to the full course
Unit 2 of 12. Unit numbers are a reading sequence reconstructed from the saved designs, not an attendance-week record.