Engineering Research Portfolio

Research, engineering, and study work in one paper-style view

Radar · Vision AI · Sensor Fusion · Embedded Signal Processing · FPGA RTL/DV

Hyeongrok Ryu · B.S. Candidate, Dankook University · Undergraduate Research Intern

Projects Papers GitHub Notion Coursework Contact

Available January 2027 · Planned ViScan booth operation and live demonstration at CES 2027

Abstract

What this portfolio shows

This page connects the engineering question, system architecture, implementation, measurements, figures, code, and follow-up work behind each project. The same reading order is used for research projects, conference papers, coursework, technical notes, and external training so that a visitor can move from the question to the actual output without searching through separate archives.

Radar · Vision AI · Sensor FusionEmbedded SystemsFPGA RTL · DVRF · PADS · Control

Research Map

Representative case studies

ECG, SCG, and FMCW radar experimental hardware and sensor setup

Radar · Biomedical Signal Processing

FMCW Radar Cardiac Timing

Aligns ECG, SCG, and non-contact FMCW radar on a beat-relative axis and analyzes morphology-based AO/AC candidate timing.

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Research pipeline connecting a PPG sensor, STM32 firmware, HRV preprocessing, and CNN Transformer evaluation

Biomedical Embedded AI

PPG–HRV Cognitive Load

Traces timing integrity from earlobe PPG acquisition through IBI/HRV feature construction and CNN+Transformer classification.

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FPGA delay-logic architecture progressing from a shift register to circular queue and memory-based design

FPGA · RTL · Digital Verification

FPGA Programmable Delay Logic

A parameterized SystemVerilog design that evolves one cycle-delay contract across shift-register, circular-queue, and memory-based Driver/Checker architectures.

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Drowsiness-monitoring prototype built with Raspberry Pi boards, an LCD, and sensor wiring

Embedded Systems · Edge Sensing

Real-Time Drowsiness Monitor

Integrates PPG and EAR vision across a two-node Raspberry Pi sensing/analysis architecture with TCP/IP and GPIO/I²C alarm paths.

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Radar PresenceFace SessionAR GuideUltrasoundrPPGReport

Vision AI · Sensor Fusion · Product Integration

ViScan Smart Mirror · CES 2027

YuNet/SFace, MediaPipe Pose, low-light/occlusion/multiple-person checks, BGT60TR13C presence and distance, camera–radar fusion, and fail-safe state gating.

Public details will be expanded after disclosure

Methodology

A shared engineering workflow

01 Question

Define the signal, interface, constraint, and failure condition.

02 Architecture

Separate sensing, processing, communication, control, and outputs.

03 Implementation

Build firmware, RTL, signal processing, models, and UI paths.

04 Verification

Use synchronized data, reference models, regression, and failure tests.

05 Communication

Publish figures, code, papers, reports, and reproducible links.

The common problem-to-evidence workflow used across the portfolio.

Results

Results visible without leaving the page

600 sECG·SCG·Radar concurrent acquisition

848Aligned cardiac beats

20 / 26 / 3FPGA regression checks and scenarios

0.85 / 0.82Paper-reported PPG-HRV AUC / F1

3Conference papers, including two first-author papers

CES 2027Planned ViScan booth operation and live demonstration

Image Gallery

Hardware, architecture, and result views

FMCW radar cardiac-signal acquisition setup with an STM32 board and ECG electrodes — Hardware used for concurrent ECG, SCG, and radar acquisition

Research architecture from PPG acquisition through HRV preprocessing and CNN evaluation — PPG acquisition, IBI/HRV preprocessing, and model-evaluation architecture

File-driven simulation waveform and timing markers for the FPGA programmable delay logic — Dynamic-delay waveform produced from the Project 3 file input

Contact sheet of the Raspberry Pi drowsiness-monitoring prototype, LCD, sensor wiring, and source views — Contact sheet of the prototype, LCD, sensor wiring, and source views

Where a publication-style architecture figure is missing, the site uses a source-based SVG/HTML diagram first. Final figures are published only after their labels, arrows, components, and values match the underlying material.

Publications

First-author conference research

CICS’25 · pp. 291–292

CNN-based HRV analysis for cognitive-task performance

PPG · STM32F411 · HRV · CNN+Transformer · Poster

KIEE Summer Conference 2026 · pp. 2413–2414

FMCW radar analysis of AO/AC candidate timing

ECG · SCG · BGT60TR13C · Beat Alignment · Poster

Coursework & Study

Engineering study paths

Electrical Engineering CourseworkCircuits, control, machines, communication, RF, and digital design STM32 · EmbeddedClock · ADC · Timer · UART · CMSIS-DSP PADS · PCBSymbol · Part · Decal · Layout · DRC · Gerber RF · Microwave · Radar50 Ω · Smith Chart · S-parameter · FMCW AI · External LearningCNN · Transformer · VAE · GAN · Diffusion · DiT All learning roadmapsChoose a domain and follow the available notes

Code · Data · Resources

Continue from the source

GitHub RepositoriesSource, firmware, RTL, notebooks, figures, and case-study files Public NotionIntegrated project, paper, coursework, and learning archive Recruitment & collaborationhnryu0515@gmail.com · LinkedIn

@misc{ryu2026engineeringportfolio,
  author = {Hyeongrok Ryu},
  title = {Engineering Research Portfolio: Radar, Vision AI, Sensor Fusion, Embedded Systems, and FPGA},
  year = {2026},
  url = {https://dororok9061.github.io/}
}