2-2 · Recovered Original
Controller Logic — VHDL Design & Portable Verification
Seven RTL blocks spanning combinational logic, an FSM, and a universal shift register were rerun with self-checking testbenches.
RTL · Machines · Power · Control · RF · Sensors
Course pages record design conditions, equations, RTL, simulation results, and remaining verification work.
Recovered originals, portable verification, recalculations, archived results, and proposals use separate status labels.
Provenance2-2 · Recovered Original
Seven RTL blocks spanning combinational logic, an FSM, and a universal shift register were rerun with self-checking testbenches.
3-1 · Source-Derived
DU, EI, and UI cores were compared for a 220/110 V, 900 W, 300 Hz transformer, leading to the UI-100 calculation case.
3-1 · Source-Derived
Surge impedance and SIL were recalculated while a non-convergent PowerWorld archive and policy figures were kept in separate evidence classes.
3-2 · Recovered Original
A 500 Hz current loop and 25 Hz speed loop are integrated with current limiting, anti-windup, and field weakening.
4-1 · Source-Derived
Microstrip, L-section and single-stub matching, a Wilkinson divider, and a branch-line hybrid are compared through theory and an existing Cadence archive.
4-1 · Research Concept
A research proposal links AESA acquisition, conventional SAR reconstruction, and physics-conditioned diffusion with a staged validation roadmap.
Personal data, local paths, license-bound originals, and third-party course material are withheld. Individual contribution to team work remains unconfirmed.