Term 2-2 · Electrical Engineering Coursework
Controller Logic — VHDL Design & Portable Verification
Seven RTL blocks spanning combinational logic, an FSM, and a universal shift register were rerun with self-checking testbenches.
RTL scope and executed tools
Seven RTL blocks spanning combinational logic, an FSM, and a universal shift register were rerun with self-checking testbenches.
- Status
- GHDL 7/7 PASS
- Evidence
- Recovered Original · Portable Reconstruction · GHDL Rerun
- Contribution
- Team Project · Individual contribution unconfirmed
Original sources versus portable verification
The source material traces a progression from logic equations through hierarchy, state machines, and register control. Because not every source file was recoverable, recovered originals and public reconstructions are separated in both the tree and the evidence labels.
- Small combinational blocks use exhaustive input-space checks.
- Sequential tests isolate reset, hold, load, both shift directions, and overlap detection.
- Public reconstructions avoid non-standard arithmetic packages and use numeric_std.
- Assertions fail CI, while successful runs emit PASS messages and VCD evidence.
Gate structure and GHDL waveforms
Recovered Vivado/XSim views
Source result views excluding student identifiers, personal data, local paths, and third-party teaching material.
VHDL entities and assertion testbenches
Regression results
Synthesis and board-test boundary
Four original Vivado 2023.2 projects and XSim contexts were recovered, but device constraints, implementation reports, and board evidence were not. Original benches contain no assertions and are labelled STIMULUS_COMPLETE; PASS belongs only to the separate self-checking GHDL 6.0.0 suite. FPGA utilization, Fmax, power, and hardware PASS are not claimed.
Sources, logs, and VCD
Links point to publishable sources, calculations, logs, and detailed provenance.