Verifying cycle-delay equivalence between shift-register and circular-queue designs
Comparing RTL architectures with one interface contract, an independent reference model, expected cycles, and 26 regression checks.
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SystemVerilog Delay Logic and DV
Compares multiple RTL structures against one cycle-delay contract and independent checker.
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Sources, tools, and prerequisites
- Tools
- SystemVerilog, Icarus Verilog, Quartus, ModelSim
- Sources
- Public RTL repository; deterministic regression logs; VCD waveform
- Prerequisites
- systemverilog, testbench