Verifying cycle-delay equivalence between shift-register and circular-queue designs

Comparison problem

Programmable delay logic emits an accepted transaction after a configured number of cycles. A shift register is direct to read but grows with depth. A circular queue implements the same behavior with read/write pointers, introducing wrap-around, occupancy, and dynamic-delay edge cases.

The comparison target is not the internal array or pointer logic. With the same input data, input valid, reset, and delay setting, both DUTs must produce the same output data, output valid, and output cycle.

Shared interface contract

The checker can describe each accepted transaction with four fields.

typedef struct packed {
  logic [DATA_W-1:0] data;
  logic              valid;
  int unsigned       accepted_cycle;
  int unsigned       expected_cycle;
} expected_txn_t;

On an accepted input cycle, it calculates expected_cycle = accepted_cycle + delay. At that cycle, output valid and data are checked together. Reset must empty the expected queue and suppress stale valid output.

For dynamic delay, the model stores the delay at acceptance. Reading the current delay later would mis-handle transactions that straddle a configuration change.

Independent reference model

Copying the DUT’s shift-register or circular-buffer logic into the model can reproduce the same defect. This model only stores transactions and expected output cycles; it has no knowledge of DUT pointers.

The driver generates reset, consecutive valid cycles, valid gaps, delay changes, and buffer wrap. The checker compares the expected queue head with both DUT outputs. A mismatch record identifies the tag, accepted cycle, expected cycle, and observed data.

26 equivalence checks

The public Project 2 regression reports 26 architecture-equivalence checks passed. The cases include DEPTH 10 and 100 with different parameters and sequences, comparing shift-register and circular-queue outputs to the reference model.

This number is the explicit checker count, not assertion count or total simulation cycles. Project 1’s 20 checks and Project 3’s three file-driven scenarios are separate results.

Reading the waveform

Data equality alone is insufficient. Output valid one cycle early, or stale data marked valid after reset, violates the contract. File-driven scenarios keep the input vector and delay changes stable across repeated regressions.

Next Quartus run

I ran the functional simulation, but I did not find Quartus synthesis, timing, resource, power, Fmax, or numerical PPA reports. I therefore make no numerical claim that the circular queue uses fewer registers or memory resources on a target FPGA. The next run will synthesize both architectures for the same device and constraints while preserving the commands and original reports.