Electrical Engineering Coursework · Controller Logic Design

Reading the Mealy 101 Detector and 8-to-1 MUX Sources

2026-08-01 · updated 2026-08-01 · Hyeongrok Ryu

My source-level review of overlapping 101 transitions and a decoder-based multiplexer from stored VHDL coursework.

Series
VHDL Digital Logic Foundations · 7
Type / level
study-note · beginner
Tools
VHDL, Vivado
01Starting from source

A checkpoint in the study sequence for this note.

02Finding 101 with three states

A checkpoint in the study sequence for this note.

03Tracing 01010101

A checkpoint in the study sequence for this note.

04Writing a standalone MUX

A checkpoint in the study sequence for this note.

A compact concept path generated from this post's table of contents.

Starting from source

I reopened the stored mealy.vhd, mealy_tb.vhd, and mux_8to1.vhd files from my 2024 coursework. I focused on the entity, architecture, and stimulus that I had written instead of the Vivado cache and generated executables.

Three-state overlapping Mealy 101 detector beside an eight-input multiplexer selection map
The left panel traces the overlapping detector; the right panel rewrites the same selection function without a decoder dependency.

Finding 101 with three states

The transition path uses three states. st0 has no useful prefix, st1 means the latest bit is 1, and st2 means the latest two bits are 10. A 1 in st2 completes 101 and asserts dout. Returning to st1 preserves that final 1 as the start of an overlapping pattern.

Current stateInput 0Input 1Output 1
st0st0st1-
st1st2st1-
st2st2st1on input 1
The st2 → st1 transition is the step that keeps overlapping detections possible.

Tracing 01010101

The stored testbench deasserts reset and applies 01010101 at 20 ns intervals. Following the table by hand completes 101 at the fourth, sixth, and eighth input positions. I did not rerun GHDL or Vivado simulation while writing this note, so these are source-level expectations rather than a new waveform result.

Saved waveform showing 01010101 input, st0 st1 st2 states, and dout pulses
I followed the saved input and state transitions together.

Writing a standalone MUX

The original mux_8to1.vhd instantiates a dec_3to8 component and combines decoded lines with AND and OR gates. The decoder source was not present in the stored bundle I reviewed. I therefore rewrote the same truth table as a dependency-free study example.

with sel select
  y <= a when "000",
       b when "001",
       c when "010",
       d when "011",
       e when "100",
       f when "101",
       g when "110",
       h when others;
This example explains the selection function; it does not alter or prove a build of the archived project.

What I will check next

On the next run I will place present_state, next_state, and dout beside the input at each clock edge. For the MUX, I will exercise all select values on the standalone version first and compare the structural version only after recovering its decoder source.

Sources used

Publication first-page preview